This invention relates to computer microprocessor design and, more particularly, to the handling of cache coherency for self-modifying code.
In an instruction set architecture that supports self-modifying code, such as that utilized by IBM® System/Z, the processor needs to ensure that, after each instruction which modifies instruction storage, subsequent instructions will be based on the updated storage. This can be achieved by discarding prefetched instructions and refetching updated instruction data.
Self-modifying code presents a special problem to modern microprocessors that utilize separate instruction and data caches. In this design, the data cache lacks the necessary information to determine whether or not data modified affects instruction storage, and thus whether prefetched instructions need to be discarded. Special interlocks between the data cache and the instruction cache should be designed to detect whether prefetched instructions should be discarded due to modified store results.
In the existing art, the interlocks to detect stores into a processor's instruction stream are known, collectively, as program-store-compare (PSC.)
The instruction cache maintains a table of addresses that have been prefetched but not completed. When the load-store unit (LSU), which contains the data cache, performs a store, the address of that store is sent to the instruction cache along a special PSC bus. If that instruction is found in the table of addresses currently prefetched, the instruction cache will send a PSC found indication to the LSU, indicating that prefetched instructions must be discarded following the store that caused the check.
The special PSC bus is often a difficult timing path, and it utilizes significant amounts of chip wiring resources. In addition, normal cache invalidate handling may have to be postponed in order to handle PSC checks of the instruction address table, which can harm system performance.